High performance system integrated circuits (IC) such as for wireless telecommunications or for internet data communications often need critical circuits including sigma delta analog to digital converters (ADC), filters, integrators, sample-holds, gain stages, delay stages, and so on, all of which contain a switched capacitor integrator circuit. These circuits require high resolution, good linearity and DC offset rejection for applications like temperature monitoring, data acquisition, and voice digitization. The key component of the integrator is its amplifier and the constancy of the summing junction. The performance is limited (1) by amplifier problems with offsets which drift with temperature, (2) by limited amplifier gain, (3) by input signal offsets and range problems, (4) by containing too many or too large components, (5) by containing components which do not track the temperature or supply characteristics of the other components, and (6) by extra components which introduce residual errors such as switch charge injection. Furthermore, on system IC's, in order to save die area and reduce chip size, it is necessary to use a circuit for multiple functions and with multiple inputs. This puts even more of a burden on the amplifier and degrades the integration of the signals.
Prior art uses various implementations of correlated double sampling (CDS) or predictive correlated double sampling (PCDS) to correct the amplifier gain and offset problems: Nagaraj, K. et al. “Reduction of finite gain effect in switched capacitor filters”, Electronics Letters, Jul. 1985. Vol. 21, No. 15. p. 644. Williams, L. et al. “A third order sigma delta modulator with extended dynamic range”, IEEE JSSC, Vol. 29, No. 3, Mar. 1994, p. 193. Huang, Y., Ferguson, P., Temes, G. “Reduced Nonlinear Distortion in circuits with correlated double sampling”, IEEE Trans on circuits and systems II, Vol. 44, No. 7, Jul. 1997, p. 593. Grilo, J., et al. “Predictive correlated double sampling switched cap integrators”, Electronics, Circuits, and Systems, 1998 IEEE International conference, Vol. 2, p. 9.
The performance of the amplifier and hence the integrator is determined by how stable (fixed) the summing junction remains when there is a change at the output of the amplifier due to the limited DC gain of the amplifier. CDS with an output holding capacitor keeps the output of the amplifier nearly constant by previously sampling and memorizing the output, thus the summing junction would also remain nearly constant; this is the same effect as if the limited amplifier gain were increased. At the same time, CDS reduces the amplifier offset problem by sampling and memorizing the offset and then later subtracting the offset from the integrated signal.
However, there are various implementation shortcomings of the prior CDS art, particularly when the techniques are implemented in a large system IC containing multiple and different kinds of inputs for a system using low power supplies. The previous solutions either address incorrectly or do not address the architecture of the amplifier which is critical for CDS (including predictive CDS, PCDS) implementation, because it would otherwise degrade the apparent gain of the amplifier through undesired charge sharing on capacitor dividers due to undesirable Miller capacitive effects occurring from the input to the output of the input transistors. This is particularly true now that two stage amplifiers are being used for low-power supply design reasons. Also the prior art does not utilize the additional advantages afforded by CDS through strategic placement of the switches and capacitors, nor do they reduce the number of components nor size of the implementations as much as possible, nor allow better temperature tracking of the components.